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| LTC3832/LTC3832-1 High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation FEATURES s s DESCRIPTIO s s s s s s s s s s s s s VOUT as Low as 0.6V High Power Switching Regulator Controller for 3.3V-5V to 0.6V-3.xV Step-Down Applications No Current Sense Resistor Required Low Input Supply Voltage Range: 3V to 8V Maximum Duty Cycle > 91% Over Temperature All N-Channel External MOSFETs Excellent Output Regulation: 1% Over Line, Load and Temperature Variations High Efficiency: Over 95% Possible Adjustable or Fixed 2.5V Output (LTC3832) Programmable Fixed Frequency Operation: 100kHz to 500kHz External Clock Synchronization Soft-Start Low Shutdown Current: <10A Overtemperature Protection Available in SO-8 and SSOP-16 Packages The LTC(R)3832/LTC3832-1 are high power, high efficiency switching regulator controllers optimized for 3.3V-5V to 0.6V-3.xV step-down applications. A precision internal reference and feedback system provide 1% output regulation over temperature, load current and line voltage variations. The LTC3832/LTC3832-1 use a synchronous switching architecture with N-channel MOSFETs. Additionally, the chip senses output current through the drain-source resistance of the upper N-channel MOSFET, providing an adjustable current limit without a current sense resistor. The LTC3832/LTC3832-1 operate with an input supply voltage as low as 3V and with a maximum duty cycle of >91% over temperature. They include a fixed frequency PWM oscillator for low output ripple operation. The 300kHz free-running clock frequency can be externally adjusted or synchronized with an external signal from 100kHz to 500kHz. In shutdown mode, the LTC3832 supply current drops to <10A. The LTC3832-1 is the SO-8 version without current limit, frequency adjustment and shutdown functions. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s CPU Power Supplies Multiple Logic Supply Generator Distributed Power Applications High Efficiency Power Conversion TYPICAL APPLICATIO 4.7F 5.1 0.1F 0.01F 15k GND 6.49k FB 4.32k 680pF G2 PVCC1 LTC3832-1 SS VCC/PVCC2 COMP G1 VIN 3V TO 7V 100 + MBR0520T1 90 80 70 60 50 VIN = 3.3V 40 0 1 2 Si9426DY 0.1F L1 3.2H VOUT 1V 9A Si9426DY + COUT 270F 2V 3832 F01 L1: SUMIDA CDEP105-3R2MC-88 COUT: PANASONIC EEFUEOD271R EFFICIENCY (%) Figure 1. High Efficiency 3.3V to 1V Power Converter U Efficiency VOUT = 2.5V VOUT = 1V 34567 LOAD CURRENT (A) 8 9 10 3832 F01b U U sn3832 3832fs 1 LTC3832/LTC3832-1 ABSOLUTE AXI U RATI GS Supply Voltage VCC ....................................................................... 9V PVCC1,2 ................................................................ 14V Input Voltage IFB, IMAX ............................................... - 0.3V to 14V SENSE+, SENSE-, FB, SHDN, FREQSET ....................... - 0.3V to VCC + 0.3V PACKAGE/ORDER I FOR ATIO TOP VIEW G1 PVCC1 PGND GND SENSE- FB SENSE+ SHDN 1 2 3 4 5 6 7 8 16 G2 15 PVCC2 14 VCC 13 IFB 12 IMAX 11 FREQSET 10 COMP 9 SS ORDER PART NUMBER TOP VIEW LTC3832EGN GN PART MARKING 3832 GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 130C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC, PVCC1, PVCC2 = 5V, unless otherwise noted. (Note 2) SYMBOL VCC PVCC VUVLO VFB VOUT VOUT PARAMETER Supply Voltage PVCC1, PVCC2 Voltage Undervoltage Lockout Voltage Feedback Voltage Output Voltage Output Load Regulation Output Line Regulation VCOMP = 1.25V q ELECTRICAL CHARACTERISTICS CONDITIONS q (Note 7) VCOMP = 1.25V q IOUT = 0A to 10A (Note 6) VCC = 4.75V to 5.25V 2 U U W WW U W (Note 1) Junction Temperature ........................................... 125C Operating Temperature Range (Note 9) .. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C ORDER PART NUMBER G1 1 PVCC1 2 GND 3 FB 4 8 7 6 5 G2 VCC/PVCC2 COMP SS LTC3832-1ES8 S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125C, JA = 130C/ W S8 PART MARKING 38321 MIN 3 3 q TYP 5 2.4 MAX 8 13.2 2.9 0.605 0.607 2.538 2.550 UNITS V V V V V V V mV mV 0.595 0.593 2.462 2.450 0.6 0.6 2.5 2.5 2 0.1 sn3832 3832fs LTC3832/LTC3832-1 The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC, PVCC1, PVCC2 = 5V, unless otherwise noted. (Note 2) SYMBOL IVCC IPVCC fOSC VSAWL VSAWH VCOMPMAX AV gm ICOMP IMAX PARAMETER Supply Current PVCC Supply Current Internal Oscillator Frequency VCOMP at Minimum Duty Cycle VCOMP at Maximum Duty Cycle Maximum VCOMP Error Amplifier Open-Loop DC Gain Error Amplifier Transconductance Error Amplifier Output Sink/Source Current IMAX Sink Current IMAX Sink Current Tempco VIH VIL IIN ISS ISSIL RSENSE RSENSEFB tr, tf tNOV DCMAX SHDN Input High Voltage SHDN Input Low Voltage SHDN Input Current Soft-Start Source Current Maximum Soft-Start Sink Current In Current Limit SENSE Input Resistance SENSE to FB Resistance Driver Rise/Fall Time Driver Nonoverlap Time Maximum G1 Duty Cycle Figure 2, PVCC1 = PVCC2 = 5V (Note 5) Figure 2, PVCC1 = PVCC2 = 5V (Note 5) Figure 2, VFB = 0V (Note 5), PVCC1 = 8V q q q ELECTRICAL CHARACTERISTICS CONDITIONS Figure 2, VSHDN = VCC VSHDN = 0V Figure 2, VSHDN = VCC (Note 3) VSHDN = 0V FREQSET Floating q q q q q MIN TYP 0.7 1 20 0.1 MAX 1.6 10 30 10 360 UNITS mA A mA A kHz V V V kHz/A dB 230 300 1.2 2.2 VFB = 0V, PVCC1 = 8V Measured from FB to COMP, SENSE + and SENSE - Floating, (Note 4) Measured from FB to COMP, SENSE + and SENSE - Floating, (Note 4) VIMAX = VCC (Note 10) VIMAX = VCC (Note 6) q q q q 2.85 10 50 1600 65 2000 100 q fOSC/IFREQSET Frequency Adjustment 2400 mho A 8 4 2.4 12 12 3300 16 20 A A ppm/C V 0.8 0.1 -8 -12 1.6 23.7 18 80 25 91 120 95 250 250 1 -18 V A A mA k k ns ns % VSHDN = VCC VSS = 0V, VIMAX = 0V, VIFB = VCC VIMAX = VCC, VIFB = 0V, VSS = VCC (Note 8), PVCC1 = 8V q q Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 3: Supply current in normal operation is dominated by the current needed to charge and discharge the external FET gates. This will vary with the LTC3832 operating frequency, operating voltage and the external FETs used. Note 4: The open-loop DC gain and transconductance from the SENSE+ and SENSE - pins to COMP pin will be (AV)(0.6/2.5) and (gm)(0.6/2.5) respectively. Note 5: Rise and fall times are measured using 10% and 90% levels. Duty cycle and nonoverlap times are measured using 50% levels. Note 6: Guaranteed by design, not subject to test. Note 7: PVCC1 must be higher than VCC by at least 2.5V for G1 to operate at 95% maximum duty cycle and for the current limit protection circuit to be active. Note 8: The current limiting amplifier can sink but cannot source current. Under normal (not current limited) operation, the output current will be zero. Note 9: The LTC3832E/LTC3832-1E are guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 10: The minimum and maximum limits for IMAX over temperature includes the intentional temperature coefficient of 3300ppm/C. This induced temperature coefficient counteracts the typical temperature coefficient of the external power MOSFET on-resistance. This results in a relatively flat current limit over temperature for the application. sn3832 3832fs 3 LTC3832/LTC3832-1 TYPICAL PERFOR A CE CHARACTERISTICS Load Regulation TA = 25C 2.53 REFER TO FIGURE 12 2.52 2.51 VOUT (V) VFB (V) ERROR AMPLIFIER TRANSCONDUCTANCE (mho) 2.54 2.50 2.49 2.48 2.47 2.46 -15 -10 5 0 OUTPUT CURRENT (A) -5 10 15 3832 G01 Output Voltage Temperature Drift ERROR AMPLIFIER SINK/SOURCE CURRENT (A) 2.55 2.54 2.53 2.52 VOUT (V) 2.51 2.50 2.49 2.48 2.47 2.46 40 30 20 VOUT (mV) 10 0 -10 -20 -30 -40 180 160 140 120 100 80 60 40 -50 -25 0 75 50 25 TEMPERATURE (C) 100 125 ERROR AMPLIFIER OPEN-LOOP GIAN (dB) REFER TO FIGURE 12 OUTPUT = NO LOAD 2.45 -50 -25 50 25 0 75 TEMPERATURE (C) Oscillator Frequency vs Temperature 360 350 FREQSET FLOATING OSCILLATOR FREQUENCY (kHz) OSCILLATOR FREQUENCY (kHz) 340 330 320 310 300 290 280 270 260 250 240 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 VSAWH - VSAWL (V) 4 UW 100 3832 G04 3832 G07 Line Regulation 0.605 0.604 0.603 0.602 0.601 0.600 TA = 25C 5 4 3 2 1 0 -1 -2 -3 -4 3 4 6 7 5 SUPPLY VOLTAGE (V) 8 3832 G02 Error Amplifier Transconductance vs Temperature 2400 2300 2200 2100 2000 1900 1800 1700 1600 - 50 - 25 0 75 50 25 TEMPERATURE (C) 100 125 VFB (mV) 0.599 0.598 0.597 0.596 0.595 -5 3832 G03 Error Amplifier Sink/Source Current vs Temperature 50 200 Error Amplifier Open-Loop Gain vs Temperature 70 65 60 55 -50 125 50 -50 -25 75 0 25 50 TEMPERATURE (C) 100 125 3830 G05 3832 G06 Oscillator Frequency vs FREQSET Input Current 700 600 500 400 300 200 100 0 -30 TA = 25C 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 10 0 20 -20 -10 FREQSET INPUT CURRENT (A) 30 3832 G08 Oscillator (VSAWH - VSAWL) vs External Sync Frequency TA = 25C 0.5 100 300 200 400 EXTERNAL SYNC FREQUENCY (kHz) 500 3832 G09 sn3832 3832fs LTC3832/LTC3832-1 TYPICAL PERFOR A CE CHARACTERISTICS Maximum G1 Duty Cycle vs Temperature 100 99 MAXIMUM G1 DUTY CYCLE (%) VFB = 0V REFER TO FIGURE 3 IMAX SINK CURRENT (A) 98 97 96 95 94 93 92 91 -50 -25 0 25 75 50 TEMPERATURE (C) 100 125 OUTPUT VOLTAGE (V) Output Current Limit Threshold vs Temperature 20 SOFT-START SOURCE CURRENT (A) 19 OUTPUT CURRENT LIMIT (A) 18 17 16 15 14 13 12 11 10 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 -10 -11 -12 -13 -14 -15 -16 - 50 - 25 0 75 50 25 TEMPERATURE (C) 100 125 SOFT-START SINK CURRENT (mA) REFER TO FIGURE 12 AND NOTE 10 OF THE ELECTRICAL CHARACTERISTICS UNDERVOLTAGE LOCKOUT THRESHOLD VOLTAGE (V) Undervoltage Lockout Threshold Voltage vs Temperature 3.0 VCC OPERATING SUPPLY CURRENT (mA) 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 PVCC SUPPLY CURRENT (mA) UW 3832 G10 3832 G13 3832 G16 IMAX Sink Current vs Temperature 20 18 16 14 12 10 8 0.5 3.0 2.5 2.0 1.5 1.0 Output Overcurrent Protection TA = 25C REFER TO FIGURE 12 6 4 - 50 - 25 0 0 75 50 25 TEMPERATURE (C) 100 125 0 2 4 6 8 10 12 14 16 18 20 OUTPUT CURRENT (A) 3832 G12 3832 G11 Soft-Start Source Current vs Temperature -8 -9 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 Soft-Start Sink Current vs (VIFB - VIMAX) TA = 25C 0 -150 -125 -100 -50 -75 VIFB - VIMAX (mV) -25 0 3832 G15 3830 G14 VCC Operating Supply Current vs Temperature 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 FREQSET FLOATING 90 80 70 60 50 40 30 20 10 0 PVCC Supply Current vs Oscillator Frequency TA = 25C G1 AND G2 LOADED WITH 6800pF, PVCC1,2 = 12V G1 AND G2 LOADED WITH 1000pF, PVCC1,2 = 5V G1 AND G2 LOADED WITH 6800pF, PVCC1,2 = 5V 0 400 100 300 200 OSCILLATOR FREQUENCY (kHz) 500 3832 G18 3832 G17 sn3832 3832fs 5 LTC3832/LTC3832-1 TYPICAL PERFOR A CE CHARACTERISTICS PVCC Supply Current vs Gate Capacitance 80 70 TA = 25C 200 180 160 PVCC SUPPLY CURRENT (mA) G1 RISE/FALL TIME (ns) 60 50 PVCC1,2 = 12V 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 GATE CAPACITANCE AT G1 AND G2 (nF) 3832 G19 PVCC1,2 = 5V PI FU CTIO S (LTC3832/LTC3832-1) G1 (Pin 1/Pin 1): Top Gate Driver Output. Connect this pin to the gate of the upper N-channel MOSFET, Q1. This output swings from PGND to PVCC1. It remains low if G2 is high or during shutdown mode. PVCC1 (Pin 2/Pin 2): Power Supply Input for G1. Connect this pin to a potential of at least VIN + VGS(ON)(Q1). This potential can be generated using an external supply or charge pump. PGND (Pin 3/Pin 3): Power Ground. Both drivers return to this pin. Connect this pin to a low impedance ground in close proximity to the source of Q2. Refer to the Layout Consideration section for more details on PCB layout techniques. The LTC3832-1 has PGND and GND tied together internally at Pin 3. GND (Pin 4/Pin 3): Signal Ground. All low power internal circuitry returns to this pin. To minimize regulation errors due to ground currents, connect GND to PGND right at the LTC3832. SENSE-, FB, SENSE+ (Pins 5, 6, 7/Pin 4): These three pins connect to the internal resistor divider and input of the error amplifier. To use the internal divider to set the output voltage to 2.5V, connect SENSE+ to the positive terminal of the output capacitor and SENSE- to the negative terminal. FB should be left floating. To use an external resistor 6 UW G1 Rise/Fall Time vs Gate Capacitance TA = 25C Transient Response 140 120 100 80 60 40 20 0 0 tf AT PVCC1,2 = 12V tr AT PVCC1,2 = 12V 1 2 3 4 5 6 7 8 9 10 GATE CAPACITANCE AT G1 AND G2 (nF) 3832 G20 VOUT 50mV/DIV tf AT PVCC1,2 = 5V tr AT PVCC1,2 = 5V ILOAD 2AV/DIV 50s/DIV 3832 G21 U U U divider to set the output voltage, float SENSE+ and SENSE- and connect the external resistor divider to FB. The internal resistor divider is not included in the LTC3832-1. SHDN (Pin 8/NA): Shutdown. A TTL compatible low level at SHDN for longer than 100s puts the LTC3832 into shutdown mode. In shutdown, G1 and G2 go low, all internal circuits are disabled and the quiescent current drops to 10A max. A TTL compatible high level at SHDN allows the part to operate normally. This pin also doubles as an external clock input to synchronize the internal oscillator with an external clock. The shutdown function is disabled in the LTC3832-1. SS (Pin 9/Pin 5): Soft-Start. Connect this pin to an external capacitor, CSS, to implement a soft-start function. If the LTC3832 goes into current limit, CSS is discharged to reduce the duty cycle. CSS must be selected such that during power-up, the current through Q1 will not exceed the current limit level. COMP (Pin 10/Pin 6): External Compensation. This pin internally connects to the output of the error amplifier and input of the PWM comparator. Use a RC + C network at this pin to compensate the feedback loop to provide optimum transient response. sn3832 3832fs LTC3832/LTC3832-1 PI FU CTIO S FREQSET (Pin 11/NA): Frequency Set. Use this pin to adjust the free-running frequency of the internal oscillator. With the pin floating, the oscillator runs at about 300kHz. A resistor from FREQSET to ground speeds up the oscillator; a resistor to VCC slows it down. IMAX (Pin 12/NA): Current Limit Threshold Set. IMAX sets the threshold for the internal current limit comparator. If IFB drops below IMAX with G1 on, the LTC3832 goes into current limit. IMAX has an internal 12A pull-down to GND. Connect this pin to the main VIN supply at the drain of Q1, through an external resistor to set the current limit threshold. Connect a 0.1F decoupling capacitor across this resistor to filter switching noise. IFB (Pin 13/NA): Current Limit Sense. Connect this pin to the switching node at the source of Q1 and the drain of Q2 through a 1k resistor. The 1k resistor is required to prevent voltage transients from damaging IFB.This pin is used for sensing the voltage drop across the upper N-channel MOSFET, Q1. VCC (Pin 14/Pin 7): Power Supply Input. All low power internal circuits draw their supply from this pin. Connect this pin to a clean power supply, separate from the main VIN supply at the drain of Q1. This pin requires a 4.7F bypass capacitor. The LTC3832-1has VCC and PVCC2 tied together at Pin 7 and requires a 10F bypass capacitor to GND. PVCC2 (Pin 15/Pin 7): Power Supply Input for G2. Connect this pin to the main high power supply. G2 (Pin 16/Pin 8): Bottom Gate Driver Output. Connect this pin to the gate of the lower N-channel MOSFET, Q2. This output swings from PGND to PVCC2. It remains low when G1 is high or during shutdown mode. To prevent output undershoot during a soft-start cycle, G2 is held low until G1 first goes high (FFBG in the Block Diagram). BLOCK DIAGRA SHDN FREQSET COMP 12A SS QSS ERR MAX POR + - VREF CC - + 2.2V QC 1.2V DISABLE ILIM + - W U U U (LTC3832) 100s DELAY INTERNAL OSCILLATOR LOGIC AND THERMAL SHUTDOWN POWER DOWN DISABLE GATE DRIVE PVCC1 S PWM R Q Q G1 PVCC2 G2 ENABLE G2 PGND VCC GND FB VREF + 10% 5.7k IFB VREF IMAX 12A BG VREF + 10% 3832 BD FFBG S R Q - + 18k SENSE + SENSE - + V PVCC1 - VCC + 2.5V sn3832 3832fs 7 LTC3832/LTC3832-1 BLOCK DIAGRA COMP 12A SS QSS ERR + VREF 2.2V QC 1.2V - TEST CIRCUITS 5V PVCC VSHDN VCC SHDN NC NC NC NC FB SS FREQSET COMP IMAX GND VCC PVCC2 PVCC1 IFB G1 6800pF LTC3832 G2 PGND SENSE - SENSE + 3832 F02 Figure 2 APPLICATIO S I FOR ATIO OVERVIEW The LTC3832/LTC3832-1 are voltage mode feedback, synchronous switching regulator controllers (see Block Diagram) designed for use in high power, low voltage step-down (buck) converters. They include an onboard PWM generator, a precision reference trimmed to 0.8%, two high power MOSFET gate drivers and all necessary 8 U + - W W (LTC3832-1) THERMAL SHUTDOWN DISABLE GATE DRIVE INTERNAL OSCILLATOR POWER DOWN PVCC1 S PWM R Q Q G1 VCC/PVCC2 G2 FFG2 S MAX POR R Q ENABLE G2 PGND - + FB VREF + 10% + V PVCC1 VREF - VCC + 2.5V VREF + 10% BG 3832 BD2 + 10F IFB VCOMP COMP LTC3832 VFB 6800pF FB IMAX GND PGND G2 6800pF 3832 F03 0.1F VCC PVCC1 PVCC2 G1 6800pF G1 RISE/FALL G2 RISE/FALL Figure 3 UU feedback and control circuitry to form a complete switching regulator circuit. The PWM loop nominally runs at 300kHz. The LTC3832 includes a current limit sensing circuit that uses the topside external N-channel power MOSFET as a current sensing element, eliminating the need for an external sense resistor. sn3832 3832fs LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO Also included in the LTC3832 is an internal soft-start feature that requires only a single external capacitor to operate. In addition, the LTC3832 features an adjustable oscillator that can free run or synchronize to external signal with frequencies from 100kHz to 500kHz, allowing added flexibility in external component selection. The LTC3832-1 does not include current limit, frequency adjustability, external synchronization and the shutdown function. THEORY OF OPERATION Primary Feedback Loop The LTC3832/LTC3832-1 sense the output voltage of the circuit at the output capacitor and feeds this voltage back to the internal transconductance error amplifier, ERR, through a resistor divider network. The error amplifier compares the resistor-divided output voltage to the internal 0.6V reference and outputs an error signal to the PWM comparator. This error signal is compared with a fixed frequency ramp waveform, from the internal oscillator, to generate a pulse width modulated signal. This PWM signal drives the external MOSFETs through the G1 and G2 pins. The resulting chopped waveform is filtered by LO and COUT which closes the loop. Loop compensation is achieved with an external compensation network at the COMP pin, the output node of the error amplifier. MAX Feedback Loop An additional comparator in the feedback loop provides high speed output voltage correction in situations where the error amplifier may not respond quickly enough. MAX compares the feedback signal to a voltage 60mV above the internal reference. If the signal is above the comparator threshold, the MAX comparator overrides the error amplifier and forces the loop to minimum duty cycle, 0%. To prevent this comparator from triggering due to noise, the MAX comparator's response time is deliberately delayed by two to three microseconds. This comparator helps prevent extreme output perturbations with fast output load current transients, while allowing the main feedback loop to be optimally compensated for stability. U Thermal Shutdown The LTC3832/LTC3832-1 have a thermal protection circuit that disables both gate drivers if activated. If the chip junction temperature reaches 150C, both G1 and G2 are pulled low. G1 and G2 remain low until the junction temperature drops below 125C, after which, the chip resumes normal operation. Soft-Start and Current Limit The LTC3832 includes a soft-start circuit that is used for start-up and current limit operation. The LTC3832-1 only has the soft-start function; the current limit function is disabled. The SS pin requires an external capacitor, CSS, to GND with the value determined by the required softstart time. An internal 12A current source is included to charge CSS. During power-up, the COMP pin is clamped to a diode drop (B-E junction of QSS in the Block Diagram) above the voltage at the SS pin. This prevents the error amplifier from forcing the loop to maximum duty cycle. The LTC3832/LTC3832-1 operate at low duty cycle as the SS pin rises above 0.6V (VCOMP 1.2V). As SS continues to rise, QSS turns off and the error amplifier takes over to regulate the output. The LTC3832 includes yet another feedback loop to control operation in current limit. Just before every falling edge of G1, the current comparator, CC, samples and holds the voltage drop measured across the external upper MOSFET, Q1, at the IFB pin. CC compares the voltage at IFB to the voltage at the IMAX pin. As the peak current rises, the measured voltage across Q1 increases due to the drop across the RDS(ON) of Q1. When the voltage at IFB drops below IMAX, indicating that Q1's drain current has exceeded the maximum level, CC starts to pull current out of CSS, cutting the duty cycle and controlling the output current level. The CC comparator pulls current out of the SS pin in proportion to the voltage difference between IFB and IMAX. Under minor overload conditions, the SS pin falls gradually, creating a time delay before current limit takes effect. Very short, mild overloads may not affect the output voltage at all. More significant overload conditions allow the SS pin to reach a steady state, and the output sn3832 3832fs W UU 9 LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO remains at a reduced voltage until the overload is removed. Serious overloads generate a large overdrive at CC, allowing it to pull SS down quickly and preventing damage to the output components. By using the RDS(ON) of Q1 to measure the output current, the current limiting circuit eliminates an expensive discrete sense resistor that would otherwise be required. This helps minimize the number of components in the high current path. The current limit threshold can be set by connecting an external resistor RIMAX from the IMAX pin to the main VIN supply at the drain of Q1. The value of RIMAX is determined by: RIMAX = (ILMAX)(RDS(ON)Q1)/IIMAX where: ILMAX = ILOAD + (IRIPPLE/2) ILOAD = Maximum load current IRIPPLE = Inductor ripple current = ( VIN - VOUT )( VOUT ) (fOSC )(LO )(VIN) fOSC = LTC3832 oscillator frequency = 300kHz LO = Inductor value RDS(ON)Q1 = On-resistance of Q1 at ILMAX IIMAX = Internal 12A sink current at IMAX The RDS(ON) of Q1 usually increases with temperature. To keep the current limit threshold constant, the internal 12A sink current at IMAX is designed with a positive temperature coefficient to provide first order correction for the temperature coefficient of RDS(ON)Q1. In order for the current limit circuit to operate properly and to obtain a reasonably accurate current limit threshold, the IIMAX and IFB pins must be Kelvin sensed at Q1's drain and source pins. In addition, connect a 0.1F decoupling capacitor across RIMAX to filter switching noise. Otherwise, noise spikes or ringing at Q1's source can cause the actual maximum current to be greater than the desired current limit set point. Due to switching noise and variation of RDS(ON), the actual current limit trip point is not highly accurate. The current limiting circuitry is primarily 10 U meant to prevent damage to the power supply circuitry during fault conditions. The exact current level where the limiting circuit begins to take effect will vary from unit to unit as the RDS(ON) of Q1 varies. Typically, RDS(ON) varies as much as 40%, and with 33% variation on the LTC3832's IMAX current, this can give a 73% variation on the current limit threshold. The RDS(ON) is high if the VGS applied to the MOSFET is low. This occurs during power up when PVCC1 is ramping up. To prevent the high RDS(ON) from activating the current limit, the LTC3832 will disable the current limit circuit if PVCC1 is less than 2.5V above VCC. To ensure proper operation of the current limit circuit, PVCC1 must be at least 2.5V above VCC when G1 is high. PVCC1 can go low when G1 is low, allowing the use of the external charge pump to power PVCC1. VIN LTC3832 RIMAX 0.1F W UU + CIN + CC 12A 12 IMAX IFB G1 1k G2 Q2 Q1 LO - 13 + VOUT COUT 3832 F04 Figure 4. Current Limit Setting Oscillator Frequency The LTC3832 includes an onboard current controlled oscillator that typically free-runs at 300kHz. The oscillator frequency can be adjusted by forcing current into or out of the FREQSET pin. With the pin floating, the oscillator runs at about 300kHz. Every additional 1A of current into/out of the FREQSET pin decreases/increases the frequency by 10kHz. The pin is internally servoed to 1.265V. The frequency can be estimated as: f = 300kHz + 1.265V - VEXT 10kHz * RFSET 1A where RFSET is a frequency programming resistor connected between FREQSET and the external voltage source VEXT. sn3832 3832fs LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO Connecting a 82k resistor from FREQSET to ground forces 15A out of the pin, causing the internal oscillator to run at approximately 450kHz. Forcing an external 20A current into FREQSET cuts the internal frequency to 100kHz. An internal clamp prevents the oscillator from running slower than about 50kHz. Tying FREQSET to V CC forces the chip to run at this minimum speed. The LTC3832-1 does not have this frequency adjustment function. Shutdown The LTC3832 includes a low power shutdown mode, controlled by the logic at the SHDN pin. A high at SHDN allows the part to operate normally. A low level at SHDN for more than 100s forces the LTC3832 into shutdown mode. In this mode, all internal switching stops, the COMP and SS pins pull to ground and Q1 and Q2 turn off. The LTC3832 supply current drops to <10A, although offstate leakage in the external MOSFETs may cause the total VIN current to be some what higher, especially at elevated temperatures. If SHDN returns high, the LTC3832 reruns a soft-start cycle and resumes normal operation. The LTC3832-1 does not have this shutdown function. External Clock Synchronization The LTC3832 SHDN pin doubles as an external clock input for applications that require a synchronized clock. An internal circuit forces the LTC3832 into external synchronization mode if a negative transition at the SHDN pin is detected. In this mode, every negative transition on the SHDN pin resets the internal oscillator and pulls the ramp signal low, this forces the LTC3832 internal oscillator to lock to the external clock frequency. The LTC3832-1 does not have this external synchronization function. The LTC3832 internal oscillator can be externally synchronized from 100kHz to 500kHz. Frequencies above 300kHz can cause a decrease in the maximum obtainable duty cycle as rise/fall time and propagation delay take up a larger percentage of the switch cycle. Circuits using these frequencies should be checked carefully in applications where operation near dropout is important--like 3.3V to 2.5V converters. The low period of this clock signal must not be >100s, or else the LTC3832 enters shutdown mode. U Figure 5 describes the operation of the conventional synchronization function. A negative transition at the SHDN pin forces the internal ramp signal low to restart a new PWM cycle. Notice that the ramp amplitude is lowered as the external clock frequency goes higher. The effect of this decrease in ramp amplitude increases the open-loop gain of the controller feedback loop. As a result, the loop crossover frequency increases and it may cause the feedback loop to be unstable if the phase margin is insufficient. To overcome this problem, the LTC3832 monitors the peak voltage of the ramp signal and adjusts the oscillator charging current to maintain a constant ramp peak. SHDN TRADITIONAL SYNC METHOD WITH EARLY RAMP TERMINATION 300kHz FREE RUNNING RAMP SIGNAL RAMP SIGNAL WITH EXT SYNC RAMP AMPLITUDE ADJUSTED LTC3832 KEEPS RAMP AMPLITUDE CONSTANT UNDER SYNC 3832 F05 W UU Figure 5. External Synchronization Operation Input Supply Considerations/Charge Pump The LTC3832 requires four supply voltages to operate: VIN for the main power input, PVCC1 and PVCC2 for MOSFET gate drive and a clean, low ripple VCC for the LTC3832 internal circuitry (Figure 6). The LTC3832-1 has the PVCC2 and VCC pins tied together inside the package (Figure 7). This pin, brought out as VCC/PVCC2, has the same low ripple requirements as the LTC3832, but must also be able to supply the gate drive current to Q2. sn3832 3832fs 11 LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO VCC PVCC2 PVCC1 VIN G1 Q1 LO INTERNAL CIRCUITRY G2 Q2 + COUT 3832 F6 LTC3832 Figure 6. LTC3832 Power Supplies VCC/PVCC2 PVCC1 VIN G1 Q1 LO VOUT INTERNAL CIRCUITRY G2 Q2 LTC3832-1 Figure 7. LTC3832-1 Power Supplies In many applications, VCC can be powered from VIN through an RC filter. This supply can be as low as 3V. The low quiescent current (typically 800A) allows the use of relatively large filter resistors and correspondingly small filter capacitors. 100 and 4.7F usually provide adequate filtering for VCC. For best performance, connect the 4.7F bypass capacitor as close to the LTC3832 VCC pin as possible. Gate drive for the top N-channel MOSFET Q1 is supplied from PVCC1. This supply must be above VIN (the main power supply input) by at least one power MOSFET VGS(ON) for efficient operation. An internal level shifter allows PVCC1 to operate at voltages above VCC and VIN, up to 14V maximum. This higher voltage can be supplied with a separate supply, or it can be generated using a charge pump. Gate drive for the bottom MOSFET Q2 is provided through PVCC2 for the LTC3832 or VCC/PVCC2 for the LTC3832-1. This supply only needs to be above the power MOSFET VGS(ON) for efficient operation. PVCC2 can also be driven from the same supply/charge pump for the PVCC1, or it can be connected to a lower supply to improve efficiency. 12 U VOUT W UU Figure 8 shows a tripling charge pump circuit that can be used to provide 2VIN and 3VIN gate drive for the external top and bottom MOSFETs respectively. These should fully enhance MOSFETs with 5V logic level thresholds. This circuit provides 3VIN - 3VF to PVCC1 while Q1 is ON and 2VIN - 2VF to PVCC2 where VF is the forward voltage of the Schottky diodes. The circuit requires the use of Schottky diodes to minimize forward drop across the diodes at start-up. The tripling charge pump circuit can rectify any ringing at the drain of Q2 and provide more than 3VIN at PVCC1; a 12V zener diode should be included from PVCC1 to PGND to prevent transients from damaging the circuitry at PVCC1 or the gate of Q1. The charge pump capacitors for PVCC1 refresh when the G2 pin goes high and the switch node is pulled low by Q2. The G2 on-time becomes narrow when LTC3832/ LTC3832-1 operates at a maximum duty cycle (95% typical), which can occur if the input supply rises more slowly than the soft-start capacitor or if the input voltage droops during load transients. If the G2 on-time gets so narrow that the switch node fails to pull completely to ground, the charge pump voltage may collapse or fail to start, causing excessive dissipation in external MOSFET, Q1. This condition is most likely with low VCC voltages and high switching frequencies, coupled with large external MOSFETs which slow the G2 and switch node slew rates. The LTC3832/LTC3832-1 overcome this problem by sensing the PVCC1 voltage when G1 is high. If PVCC1 is less than 2.5V above VCC, the maximum G1 duty cycle is reduced to 70% by clamping the COMP pin at 1.8V (QC in the Block DZ 12V 1N5242 1N5817 1N5817 0.1F 0.1F Q1 LO VOUT G2 VIN 1N5817 + COUT 3832 F7 10F PVCC2 PVCC1 G1 + Q2 COUT 3832 F08 LTC3832 Figure 8. Tripling Charge Pump sn3832 3832fs LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO Diagram). This increases the G2 on-time and allows the charge pump capacitors to be refreshed. For applications using an external supply to PVCC1, this supply must also be higher than VCC by at least 2.5V to ensure normal operation. For applications with a 5V or higher VIN supply, PVCC2 can be tied to VIN if a logic level MOSFET is used. PVCC1 can be supplied using a doubling charge pump as shown in Figure 9. This circuit provides 2VIN - VF to PVCC1 while Q1 is ON. VIN OPTIONAL USE FOR VIN 7V DZ 12V 1N5242 PVCC2 PVCC1 G1 MBR0530T1 0.1F Q1 LO VOUT G2 Q2 LTC3832 Figure 9. Doubling Charge Pump Power MOSFETs Two N-channel power MOSFETs are required for most LTC3832 circuits. These should be selected based primarily on threshold voltage and on-resistance considerations. Thermal dissipation is often a secondary concern in high efficiency designs. The required MOSFET threshold should be determined based on the available power supply voltages and/or the complexity of the gate drive charge pump scheme. In 3.3V input designs where an auxiliary 12V supply is available to power PVCC1 and PVCC2, standard MOSFETs with RDS(ON) specified at VGS = 5V or 6V can be used with good results. The current drawn from this supply varies with the MOSFETs used and the LTC3832's operating frequency, but is generally less than 50mA. LTC3832 applications that use 5V or lower VIN voltage and a doubling/tripling charge pump to generate PVCC1 and PVCC2, do not provide enough gate drive voltage to fully U enhance standard power MOSFETs. Under this condition, the effective MOSFET RDS(ON) may be quite high, raising the dissipation in the FETs and reducing efficiency. Logic level FETs are the recommended choice for 5V or lower voltage systems. Logic level FETs can be fully enhanced with a doubler/tripling charge pump and will operate at maximum efficiency. After the MOSFET threshold voltage is selected, choose the RDS(ON) based on the input voltage, the output voltage, allowable power dissipation and maximum output current. In a typical LTC3832 circuit, operating in continuous mode, the average inductor current is equal to the output load current. This current flows through either Q1 or Q2 with the power dissipation split up according to the duty cycle: + COUT 3832 F09 W UU VOUT VIN V V -V DC(Q2) = 1 - OUT = IN OUT VIN VIN DC(Q1) = The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R. RDS(ON)Q1 = RDS(ON)Q2 = PMAX(Q1) DC(Q1) * (ILOAD PMAX(Q2 ) )2 = = VIN * PMAX(Q1) VOUT * (ILOAD )2 VIN * PMAX(Q2 ) ( VIN - VOUT ) * (ILOAD)2 DC(Q2) * (ILOAD)2 PMAX should be calculated based primarily on required efficiency or allowable thermal dissipation. A typical high efficiency circuit designed for 3.3V input and 2.5V at 10A output might allow no more than 3% efficiency loss at full load for each MOSFET. Assuming roughly 90% efficiency at this current level, this gives a PMAX value of: (2.5V)(10A/0.9)(0.03) = 0.83W per FET and a required RDS(ON) of: (3.3V) * (0.83W) = 0.011 (2.5V)(10 A)2 (3.3V) * (0.83W) = 0.034 RDS(ON)Q2 = (3.3V - 2.5V)(10 A)2 RDS(ON)Q1 = sn3832 3832fs 13 LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO Note that the required RDS(ON) for Q2 is roughly three times that of Q1 in this example. Note also that while the required RDS(ON) values suggest large MOSFETs, the power dissipation numbers are only 0.83W per device or less; large TO-220 packages and heat sinks are not necessarily required in high efficiency applications. Siliconix Si4410DY or International Rectifier IRF7413 (both in SO-8) or Siliconix SUD50N03-10 (TO-252) or ON Semiconductor MTD20N03HDL (DPAK) are small footprint surface mount devices with RDS(ON) values below 0.03 at 5V of VGS that work well in LTC3832 circuits. Using a higher PMAX value in the RDS(ON) calculations generally decreases the MOSFET cost and the circuit efficiency and increases the MOSFET heat sink requirements. Table 1 highlights a variety of power MOSFETs for use in LTC3832 applications. Inductor Selection The inductor is often the largest component in an LTC3832 design and must be chosen carefully. Choose the inductor value and type based on output slew rate requirements. The maximum rate of rise of inductor current is set by the inductor's value, the input-to-output voltage differential and Table 1. Recommended MOSFETs for LTC3832 Applications RDS(ON) AT 25C (m) 19 20 35 8 10 9 19 28 37 PARTS Siliconix SUD50N03-10 TO-252 Siliconix Si4410DY SO-8 ON Semiconductor MTD20N03HDL DPAK Fairchild FDS6670A S0-8 Fairchild FDS6680 SO-8 ON Semiconductor MTB75N03HDL DD PAK IR IRL3103S DD PAK IR IRLZ44 TO-220 Fuji 2SK1388 TO-220 Note: Please refer to the manufacturer's data sheet for testing conditions and detailed information. sn3832 3832fs 14 U the LTC3832's maximum duty cycle. In a typical 3.3V input, 2.5V output application, the maximum rise time will be: W UU DCMAX * ( VIN - VOUT ) 0.76 A = LO LO s where LO is the inductor value in H. With proper frequency compensation, the combination of the inductor and output capacitor values determine the transient recovery time. In general, a smaller value inductor improves transient response at the expense of ripple and inductor core saturation rating. A 1H inductor has a 0.76A/s rise time in this application, resulting in a 6.6s delay in responding to a 5A load current step. During this 6.6s, the difference between the inductor current and the output current is made up by the output capacitor. This action causes a temporary voltage droop at the output. To minimize this effect, the inductor value should usually be in the 1H to 5H range for most 3.3V input LTC3832 circuits. To optimize performance, different combinations of input and output voltages and expected loads may require different inductor values. Once the required value is known, the inductor core type can be chosen based on peak current and efficiency RATED CURRENT (A) 15 at 25C 10 at 100C 10 at 25C 8 at 70C 20 at 25C 16 at 100C 13 at 25C 11.5 at 25C 75 at 25C 59 at 100C 64 at 25C 45 at 100C 50 at 25C 36 at 100C 35 at 25C TYPICAL INPUT CAPACITANCE CISS (pF) 3200 2700 880 3200 2070 4025 1600 3300 1750 JC (C/W) 1.8 TJMAX (C) 175 150 1.67 25 25 1 1.4 1 2.08 150 150 150 150 175 175 150 LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO requirements. Peak current in the inductor will be equal to the maximum output load current plus half of the peak-topeak inductor ripple current. Ripple current is set by the inductor value, the input and output voltage and the operating frequency. The ripple current is approximately equal to: IRIPPLE = ( VIN - VOUT ) * ( VOUT ) fOSC * LO * VIN fOSC = LTC3832 oscillator frequency = 300kHz LO = Inductor value Solving this equation with our typical 3.3V to 2.5V application with a 1H inductor, we get: (3.3V - 2.5V) * 2.5V = 2AP-P 300kHz * 1H * 3.3V Peak inductor current at 10A load: 10A + (2A/2) = 11A The ripple current should generally be between 10% and 40% of the output current. The inductor must be able to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. Note that in circuits not employing the current limit function, the current in the inductor may rise above this maximum under short-circuit or fault conditions; the inductor should be sized accordingly to withstand this additional current. Inductors with gradual saturation characteristics are often the best choice. Input and Output Capacitors A typical LTC3832 design places significant demands on both the input and the output capacitors. During normal steady load operation, a buck converter like the LTC3832 draws square waves of current from the input supply at the switching frequency. The peak current value is equal to the output load current plus 1/2 the peak-to-peak ripple current. Most of this current is supplied by the input bypass capacitor. The resulting RMS current flow in the input capacitor heats it and causes premature capacitor failure in extreme cases. Maximum RMS current occurs with 50% PWM duty cycle, giving an RMS current value equal U to IOUT/2. A low ESR input capacitor with an adequate ripple current rating must be used to ensure reliable operation. Note that capacitor manufacturers' ripple current ratings are often based on only 2000 hours (3 months) lifetime at rated temperature. Further derating of the input capacitor ripple current beyond the manufacturer's specification is recommended to extend the useful life of the circuit. Lower operating temperature has the largest effect on capacitor longevity. The output capacitor in a buck converter under steadystate conditions sees much less ripple current than the input capacitor. Peak-to-peak current is equal to inductor ripple current, usually 10% to 40% of the total load current. Output capacitor duty places a premium not on power dissipation but on ESR. During an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the LTC3832 adjusts the inductor current to the new value. ESR in the output capacitor results in a step in the output voltage equal to the ESR value multiplied by the change in load current. An 5A load step with a 0.05 ESR output capacitor results in a 250mV output voltage shift; this is 10% of the output voltage for a 2.5V supply! Because of the strong relationship between output capacitor ESR and output load transient response, choose the output capacitor for ESR, not for capacitance value. A capacitor with suitable ESR will usually have a larger capacitance value than is needed to control steady-state output ripple. Electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and ESR can be used effectively in LTC3832 applications. OS-CON electrolytic capacitors from Sanyo and other manufacturers give excellent performance and have a very high performance/size ratio for electrolytic capacitors. Surface mount applications can use either electrolytic or dry tantalum capacitors. Tantalum capacitors must be surge tested and specified for use in switching power supplies. Low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. Other capacitors that can be used include the Sanyo POSCAP and MV-WX series. A common way to lower ESR and raise ripple current capability is to parallel several capacitors. A typical sn3832 3832fs W UU 15 LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO LTC3832 application might exhibit 5A input ripple current. Sanyo OS-CON capacitors, part number 10SA220M (220F/10V), feature 2.3A allowable ripple current at 85C; three in parallel at the input (to withstand the input ripple current) meet the above requirements. Similarly, Sanyo POSCAP 4TPB470M (470F/4V) capacitors have a maximum rated ESR of 0.04; three in parallel lower the net output capacitor ESR to 0.013. Feedback Loop Compensation The LTC3832 voltage feedback loop is compensated at the COMP pin, which is the output node of the error amplifier. The feedback loop is generally compensated with an RC + C network from COMP to GND as shown in Figure 10a. 7 SENSE + LTC3832 COMP C2 R2 VFB 10 RC CC C1 ERR R1 SENSE - VREF 3832 F10a Figure 10a. Compensation Pin Hook-Up fZ LOOP GAIN fSW = LTC3832 SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY LOOP GAIN 20dB/DECADE 20dB/DECADE fCO fP fLC fESR fCO FREQUENCY fLC fZC2 fESR 3832 F10b Figure 10b. Bode Plot of the LTC3832 Overall Transfer Function 16 U Loop stability is affected by the values of the inductor, the output capacitor, the output capacitor ESR, the error amplifier transconductance and the error amplifier compensation network. The inductor and the output capacitor create a double pole at the frequency: fLC = 1/ 2 (LO )(COUT ) W - + UU [ ] The ESR of the output capacitor and the output capacitor value form a zero at the frequency: fESR = 1/ [2 (ESR)(COUT )] The compensation network used with the error amplifier must provide enough phase margin at the 0dB crossover frequency for the overall open-loop transfer function. The zero and pole from the compensation network are: fZ = 1/[2(RC)(CC)] and fP = 1/[2(RC)(C1)] respectively Figure 10b shows the Bode plot of the overall transfer function. When low ESR output capacitors (Sanyo OS-CON) are used, the ESR zero can be high enough in frequency that it provides little phase boost at the loop crossover frequency. As a result, the phase margin becomes inadequate and the load transient is not optimized. To resolve this problem, a small capacitor can be connected 6 5 fSW = LTC3832 SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY fZ fP fPC2 FREQUENCY 3832 F10c Figure 10c. Bode Plot of the LTC3832 Overall Transfer Function Using a Low ESR Output Capacitor sn3832 3832fs LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO between the top of the resistor divider network and the V FB pin to create a pole-zero pair in the loop compensation. The zero location is prior to the pole location and thus, phase lead can be added to boost the phase margin at the loop crossover frequency. The pole and zero locations are located at: fZC2 = 1/[2(R2)(C2)] and fPC2 = 1/[2(R1||R2)(C2)] where R1||R2 is the parallel combination resistance of R1 and R2. For low R2/R1 ratios there is not much separation between fCZ2 and fPC2. In this case, use multiple capacitors with a high ESR * capacitance product to bring fESR close to fCO. Choose C2 so that the zero is located at a lower frequency compared to fCO and the pole location is high enough that the closed loop has enough phase margin for stability. Figure 10c shows the Bode plot using phase lead compensation around the LTC3832 resistor divider network. Although a mathematical approach to frequency compensation can be used, the added complication of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations, all suggest a more practical empirical method. This can be done by injecting a transient current at the load and using an RC network box to iterate toward the final values, or by obtaining the optimum loop response using a network analyzer to find the actual loop poles and zeros. Table 2 shows the suggested compensation component value for 3.3V to 2.5V applications based on Sanyo OS-CON 4SP820M low ESR output capacitors. Table 2. Recommended Compensation Network for 3.3V to 2.5V Applications Using Multiple Paralleled 820F Sanyo OS-CON 4SP820M Output Capacitors L1 (H) 1.2 1.2 1.2 2.4 2.4 2.4 4.7 4.7 4.7 COUT (F) 1640 2460 4100 1640 2460 4100 1640 2460 4100 RC (k) 9.1 15 24 22 33 43 33 56 91 CC (nF) 4.7 4.7 3.3 4.7 3.3 2.2 3.3 2.2 2.2 C1 (pF) 560 330 270 330 220 180 120 100 100 C2 (pF) 1500 1500 1500 1500 1500 1500 1500 1500 1500 U Table 3 shows the suggested compensation component values for 3.3V to 2.5V applications based on 470F Sanyo POSCAP 4TPB470M output capacitors. Table 3. Recommended Compensation Network for 3.3V to 2.5V Applications Using Multiple Paralleled 470F Sanyo POSCAP 4TPB470M Output Capacitors L1 (H) 1.2 1.2 1.2 2.4 2.4 2.4 4.7 4.7 4.7 COUT (F) 1410 2820 4700 1410 2820 4700 1410 2820 4700 RC (k) 13 27 51 33 62 82 62 150 220 CC (F) 0.0047 0.0018 0.0015 0.0033 0.0022 0.001 0.0022 0.0015 0.0015 C1 (pF) 100 56 47 56 15 39 15 10 2 W UU Table 4 shows the suggested compensation component values for 3.3V to 2.5V applications based on 1500F Sanyo MV-WX output capacitors. Table 4. Recommended Compensation Network for 3.3V to 2.5V Applications Using Multiple Paralleled 1500F Sanyo MV-WX Output Capacitors L1 (H) 1.2 1.2 1.2 2.4 2.4 2.4 4.7 4.7 4.7 COUT (F) 4500 6000 9000 4500 6000 9000 4500 6000 9000 RC (k) 39 56 82 82 100 150 120 220 220 CC (F) 0.0042 0.0033 0.0033 0.0033 0.0022 0.0022 0.0022 0.0022 0.0015 C1 (pF) 180 120 100 82 56 68 39 27 33 LAYOUT CONSIDERATIONS When laying out the printed circuit board, use the following checklist to ensure proper operation of the LTC3832. These items are also illustrated graphically in the layout diagram of Figure 11. The thicker lines show the high current paths. Note that at 10A current levels or above, current density in the PC board itself is a serious concern. Traces carrying high current should be as wide as possible. For example, a PCB fabricated with 2oz copper requires a minimum trace width of 0.15" to carry 10A. sn3832 3832fs 17 LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO 1. In general, layout should begin with the location of the power devices. Be sure to orient the power circuitry so that a clean power flow path is achieved. Conductor widths should be maximized and lengths minimized. After you are satisfied with the power path, the control circuitry should be laid out. It is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths. 2. The GND and PGND pins should be shorted directly at the LTC3832. This helps to minimize internal ground disturbances in the LTC3832 and prevent differences in ground potential from disrupting internal circuit operation. This connection should then tie into the ground plane at a single point, preferably at a fairly quiet point in the circuit such as close to the output capacitors. This is not always practical, however, due to physical constraints. Another reasonably good point to make this connection is between the output capacitors and the source connection of the bottom MOSFET Q2. Do not tie this single point ground in the trace run between the Q2 source and the input capacitor ground, as this area of the ground plane will be very noisy. PVCC 100 + 4.7F 1F GND NC VCC PVCC2 PVCC1 LTC3832 FREQSET SHDN COMP C1 RC CC CSS GND SS G1 IMAX IFB SENSE + G2 FB SENSE - GND PGND NC PGND Figure 11. Typical Schematic Showing Layout Considerations 18 U 3. The small-signal resistors and capacitors for frequency compensation and soft-start should be located very close to their respective pins and the ground ends connected to the signal ground pin through a separate trace. Do not connect these parts to the ground plane! 4. The VCC, PVCC1 and PVCC2 decoupling capacitors should be as close to the LTC3832 as possible. The 4.7F and 1F bypass capacitors shown at VCC, PVCC1 and PVCC2 will help provide optimum regulation performance. 5. The (+) plate of CIN should be connected as close as possible to the drain of the upper MOSFET, Q1. An additional 1F ceramic capacitor between VIN and power ground is recommended. 6. The SENSE and VFB pins are very sensitive to pickup from the switching node. Care should be taken to isolate SENSE and VFB from possible capacitive coupling to the inductor switching signal. Connecting the SENSE+ and SENSE - close to the load can significantly improve load regulation. 7. Kelvin sense IMAX and IFB at Q1's drain and source pins. VIN 1F 0.1F Q1A 1k Q1B LO VOUT Q2 W UU + CIN + COUT PGND 3832 F11 sn3832 3832fs LTC3832/LTC3832-1 APPLICATIO S I FOR ATIO OPTIONAL DZ 12V 1N5242 1N5817 + 100 10F PVCC2 VCC 4.7F 1F 0.01F NC SHDN C1 180pF RC 18k CC 1500pF SS PVCC1 G1 IMAX LTC3832 IFB FREQSET SHDN COMP G2 PGND GND SENSE + SENSE - FB NC CIN: SANYO 6TPB330M COUT: SANYO 4TPB470M D1: MBRS330T3 LO: SUMIDA CDEP105-1R3-MC-S Q1A, Q1B, Q2: FAIRCHILD FDS6670A 3832 F12a + Figure 12. Typical 3.3V to 2.5V, 14A Application 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 TA = 25C VIN = 3.3V VOUT = 2.5V REFER TO FIGURE 12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LOAD CURRENT (A) 3832 F12b U + CIN 330F x2 VIN 3.3V 1N5817 1N5817 5.6k 0.1F 0.1F 0.1F Q1A, Q1B 2 IN PARALLEL LO 1.3H D1 VOUT 2.5V 14A 1k Q2 W UU + COUT 470F x3 Efficiency vs Load Current sn3832 3832fs 19 LTC3832/LTC3832-1 TYPICAL APPLICATIO S Typical 3.3V to 5V, 5A Synchronous Boost Converter VIN 3.3V + CIN 330F 10F 10 10F PVCC1 VCC PVCC2 IMAX LTC3832 IFB FREQSET SHDN COMP SENSE + SENSE- NC G1 PGND GND G2 FB 2.2F 0.47F NC SHUTDOWN C1 68pF RC 6.8k CC 0.01F NC 20 U MBR0520 MBR0520 5m 5.6k 0.1F 100 0.1F LO 1.3H MBR330T3 Q2 Q1 10F VOUT 5V 5A SS + 93.1k 1% 12.7k 1% 3832 TA03 COUT 330F x2 CIN, COUT: SANYO POSCAP 6TPB330M LO: SUMIDA CDEP105-1R3-MC-S Q1, Q2: SILICONIX Si4864DY sn3832 3832fs LTC3832/LTC3832-1 TYPICAL APPLICATIO S Typical 3.3V to - 5V, 5A Positive-to-Negative Converter 100 1F 10F PVCC2 VCC DZ 8.2V 1F 0.01F NC SHUTDOWN SS PVCC1 G1 IMAX LTC3832 IFB FREQSET SHDN COMP RC 15k NC SENSE + FB PGND GND CIN, COUT: SANYO POSCAP 6TPB330M LO: SUMIDA CDEP105-1R3-MC-S Q1, Q2: SILICONIX Si7440DP 12.7k 1% 3832 TA04 C1 180pF CC 1.5nF U VIN 3.3V + MBR0520 CIN 330F 3.5k 0.1F 0.1F Q1 LO 1.3H Q2 13V 1k G2 + 10F COUT 330F 93.1k 1% SENSE- NC VOUT -5V 5A sn3832 3832fs 21 LTC3832/LTC3832-1 PACKAGE DESCRIPTIO .254 MIN .0165 .0015 RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP .053 - .068 (1.351 - 1.727) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249) 22 U GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 TYP .008 - .012 (0.203 - 0.305) .0250 (0.635) BSC GN16 (SSOP) 0502 sn3832 3832fs LTC3832/LTC3832-1 PACKAGE DESCRIPTIO .050 BSC 8 N N .245 MIN .160 .005 .228 - .244 (5.791 - 6.197) 1 .030 .005 TYP 2 3 N/2 RECOMMENDED SOLDER PAD LAYOUT .010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254) 0- 8 TYP .016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .045 .005 .189 - .197 (4.801 - 5.004) NOTE 3 7 6 5 .150 - .157 (3.810 - 3.988) NOTE 3 N/2 1 2 3 4 .053 - .069 (1.346 - 1.752) .004 - .010 (0.101 - 0.254) .014 - .019 (0.355 - 0.483) TYP .050 (1.270) BSC SO8 0502 sn3832 3832fs 23 LTC3832/LTC3832-1 TYPICAL APPLICATIO 100 1F + 4.7F 0.1F 0.01F NC SHUTDOWN C1 180pF RC 18k CC 0.01F RELATED PARTS PART NUMBER LTC1530 LTC1628 LTC1702 LTC1705 LTC1709 LTC1736 LTC1753 LTC1773 LTC1778 LTC1873 LTC1876 LTC1929 LTC3713 LTC3831 DESCRIPTION High Power Synchronous Switching Regulator Controller Dual High Efficiency 2-Phase Synchronous Step-Down Controller Dual High Efficiency 2-Phase Synchronous Step-Down Controller Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID Plus LDO 2-Phase, 5-Bit Desktop VID Synchronous Step-Down Controller Synchronous Step-Down Controller with 5-Bit Mobile VID Control 5-Bit Desktop VID Programmable Synchronous Switching Regulator Synchronous Step-Down Controller in MS10 Wide Operating Range/Step-Down Controller, No RSENSE Dual Synchronous Switching Regulator with 5-Bit Desktop VID 2-Phase, Dual Step-Down Synchronous Controller with Integrated Step-Up DC/DC Regulator 2-Phase, Synchronous High Efficiency Converter with Mobile VID Low Input Voltage, High Power, No RSENSE, Step-Down Synchronous Controller High Power Synchronous Switching Regulator Controller for DDR Memory Termination COMMENTS SO-8 with Current Limit. No RSENSETM Required Constant Frequency, Standby 5V and 3.3V LDOs, 3.5V VIN 36V 550kHz, 25MHz GBW Voltage Mode, VIN 7V, No RSENSE Provides CPU Core, I/O and CLK Supplies for Portable Systems Current Mode, VIN to 36V, IOUT Up to 42A Fault Protection, Power Good, 3.5V to 36V Input, Current Mode 1.3V to 3.5V Programmable Output Using Internal 5-Bit DAC Up to 95% Efficiency, 550kHz, 2.65V VIN 8.5V, 0.8V VOUT VIN, Synchronizable to 750kHz VIN Up to 36V, Current Mode, Power Good 1.3V to 3.5V Programmable Core Output Plus I/O Output Step-Down DC/DC Conversion from 3VIN, Minimum CIN and COUT, Uses Logic-Level N-Channel MOSFETs Current Mode Ensures Accurate Current Sensing VIN Up to 36V, IOUT Up to 40A Minimum VIN: 1.5V, Uses Standard Logic-Level N-Channel MOSFETs VOUT Tracks 1/2 of VIN or External Reference No RSENSE is a trademark of Linear Technology Corporation. 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U Typical 5V to 3.3V, 10A Application 5V + MBR0530T1 + PVCC2 VCC SS PVCC1 G1 IMAX LTC3832 IFB FREQSET SHDN COMP G2 PGND GND SENSE + SENSE- NC FB NC Q2 1k 0.1F 20k 0.1F CIN 330F x2 Q1A, Q1B 2 IN PARALLEL LO 1.3H + COUT 470F x3 3.3V 10A 45k 1% 10k 1% CIN: SANYO 6TPB330M COUT: SANYO 4TPB470M LO: SUMIDA CDEP105-1R3-MC-S Q1A, Q1B, Q2: ON SEMICONDUCTOR MTD20N03HDL 3830 TA02 sn3832 3832fs LT/TP 1002 2K * PRINTED IN USA www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2002 |
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